1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same. In particular, the present invention relates to a semiconductor device with a trench gate power MOSFET construction that is used in a power supply circuit or the like, and to a method of manufacturing the same.
2. Background Art
Trench gate power MOSFETs have been widely used in recent years in a variety of power supply apparatuses, such as DC-DC converters. FIGS. 51A and 51B show one example of a semiconductor device that has a trench gate power MOSFET construction according to the background art, with FIG. 51A being an overhead view of the semiconductor device and FIG. 51B being a cross-sectional view taken along the line A-A in FIG. 51A. In these drawings, numerals 100a to 100e are cells, numeral 110 is a trench, numeral 111 is a gate electrode film, numeral 117 is an N+ type silicon substrate, numeral 118 is an N− epitaxial layer, numeral 119 is a P type body layer, numeral 120 is a P+type diffusion region, numeral 121 is an N+type source region, numeral 122 is an interlayer dielectric, numeral 124 is a source electrode film, numeral 125 is a drain electrode film, numeral 127 is a gate insulating film, and numeral 141 is an upper insulating film.
As shown by the cells 100a to 100e in FIG. 51A, the present semiconductor device is formed with a large number of cells that are arranged in a hound's-tooth check-like pattern on the surface of the semiconductor device. As shown by cell 100a, for example, each cell is formed with an N+type source region 121 surrounding a P+type diffusion region.
As shown in FIG. 51B, the cross-sectional form of the present semiconductor device is such that an N− epitaxial layer 118 is formed on top of an N+ type silicon substrate 117, with a P type body layer 119 being formed on top of the N− epitaxial layer 118. P+type diffusion regions 120 and N+type source regions 121 are formed in this P type body layer 119. Trenches 110 that pass through the P type body layer 119 and are deep enough to reach into the N− epitaxial layer 118 are also formed between the cells 100a to 100e. 
The trenches 110 provide an opening to the P type body layer 119 and reach into the N− epitaxial layer 118. A gate insulating film 127 is formed on the side surfaces and bottom surfaces of these trenches 110, with a gate electrode film 111 being formed in the spaces surrounded by the gate insulating film 127. An upper insulating film 141 is formed on top of the gate insulating film 127 and the gate electrode film 111. An interlayer dielectric 122 is also formed on top of the upper insulating film 141 and parts of the N+type source region 121.
A source electrode film 124 is formed on top of the P+type diffusion region 120, the N+ type source region 121, and the interlayer dielectric 122. A drain electrode film 125 is also formed on the other surface of the N+ type silicon substrate 117.
In a semiconductor device of the above construction, when a voltage is applied between the source electrode film 124 and the drain electrode film 125 and a voltage that is equal to or greater than a predetermined threshold voltage is simultaneously applied between the gate electrode film 111 and the source electrode film 124, an inversion layer is formed in the P type body layer 119 in a boundary region adjacent to the gate insulating film 127, thereby creating a channel. As a result, an electric current flows through this channel from the drain electrode film 125 to the source electrode film 124.
On the other hand, with a semiconductor device of the above construction, the trenches 110 have to be deeply formed in order to make the bottom parts of the gate insulating film 127 thicker than the other parts and so ensure that a suitable breakdown voltage is achieved for the gate insulating film 127. For this purpose, as shown in FIG. 51B, the trenches 110 are produced with a large depth D so as to provide sufficient space for making the bottom parts of the gate insulating film 127 thick. If the trenches 110 are deeply formed, an increase can be made in the area of the outer surface of the gate insulating film 127, making it possible to reduce the On resistance Ron.
However, when the area of the outer surface of the gate insulating film 127 is increased, this also results in an increase in the capacitance Crss between the gate electrode film 111 and the N− epitaxial layer 118, which worsens the switching characteristics of the semiconductor device. Also, increasing the depth D can lead to problems such as an electrical field being concentrated at a specific part of the gate insulating film 127 when a voltage is applied between the source electrode film 124 and the drain electrode film 125.